The invention relates to the field of lattice-mismatched semiconductor material integration, and in particular to the integration of SiGe materials onto a Si substrate.
As many lattice-matched devices and circuits mature, interest in lattice-mismatched semiconductors, devices, and circuits has increased. There are two driving forces behind the increased commercial interest: integration and component performance. Integrating dissimilar semiconductor materials on a common substrate allows the designer to improve performance, lower cost, and increase reliability. Thus, the most susceptible applications to this initial advance will be systems that require multiple types of semiconductor materials currently packaged separately and combined in a more conventional packaging solution. Examples of these applications are III-V materials integration on Si, and SiGe circuit integration with Si CMOS. Such single-chip systems are anticipated to have wide application in communication technologies, particularly wireless communications technologies.
The utility of combined dissimilar semiconductors relies on the quality of the resulting material. Large lattice-mismatch between the substrate and deposited layer creates stress during material deposition, creating many defects in the deposited layer, resulting in poor material quality and limited performance. To control threading dislocation densities in high mismatched deposited layers, there are only two well-established techniques: substrate patterning and composition grading. In the case of substrate patterning, the idea utilizes the knowledge that the threading dislocations are a necessity of geometry, i.e. that a dislocation cannot end in a crystal. If the free edge is brought closer to another free edge by patterning the substrate into smaller growth areas, then it is possible to reduce threading dislocation densities. This technique works best for low mismatched systems in which dislocation nucleation is not rampant; however, it will reduce threading dislocation densities in high mismatched systems as well.
The other well-established technique is the use of composition graded layers. One can imagine that to reach a large total mismatch, a series of low mismatched interfaces could achieve great relaxation but keep threading dislocation densities low. This result is possible if each layer becomes substantially relaxed and is able to reuse the threading dislocations from the layer below. This method was long ago applied in an empirical way to GaAsP LEDs grown on lattice-mismatched GaAs substrates. However, after the GaAsP process was transferred to manufacturing, most of the subsequent lattice-mismatch research focused on single mismatched interfaces. The driving force for lattice-mismatched materials in applications decreased as AlGaAs/GaAs structures and InGaAsP/InP structures dominated optoelectronic and electronic device applications. Until these materials systems were fully exploited, the implementation of high mismatched layers seemed unnecessary.
A renewed interest in graded layers has occurred due to the increased demand for novel components, as well as an increased demand for increased integration. The advances in relaxed graded SiGe have shown that SiGe devices based on relaxed SiGe on Si, and the integration of III-V materials on Si using intermediate relaxed SiGe graded layers are possible. Thus, relaxed, graded SiGe layers can act as the material bridge between SiGe devices and/or III-V devices and Si substrates.
These materials advances, however, are incomplete unless a proper process sequence can be found to create these relaxed layers and subsequent devices with relatively standard Si circuit processing. A critical view of electronic and optoelectronic systems shows that the main data processing in many applications can be executed in Si CMOS circuits, which dominate the semiconductor industry today. To create a new realm of Si-based single-chip systems, a structure and process to combine Si CMOS circuits with the materials advances in relaxed graded SiGe mentioned above, is necessary.